The present invention relates to a scan flip-flop circuit and, more particularly, to a scan flip-flop circuit used to perform a scan test for a semiconductor integrated circuit.
A scan test for detecting a fault of a semiconductor integrated circuit has used a scan flip-flop circuit, as disclosed in Japanese Patent Laid-Open No. 1-96573. FIG. 5 shows a conventional scan flip-flop circuit.
In FIG. 5, the scan flip-flop circuit comprises a selector 40 on the input stage, a master latch 41 for receiving an output from the selector 40, a slave latch 43 for receiving an output from the master latch 41, and a clock unit 44.
The selector 40 comprises a transmission gate 401 for enabling/disabling (on/off) an input signal D, and a transmission gate 402 for enabling/disabling an input signal SIN. The outputs of the transmission gates 401 and 402 are commonly connected to the subsequent master latch 41. The selector 40 selects either one of the data input signal D input as a normal logic signal in normal operation and the scan input signal SIN input as a scan logic signal in a scan test.
The clock unit 44 generates a signal for controlling each transmission gate formed at the corresponding portion in the scan flip-flop circuit on the basis of a clock signal CLK and control signal SEL. In the clock unit 44, the clock signal CLK is input to an inverter 441 to output the logically inverted signal as a clock signal AB. The clock signal AB is input to an inverter 442 to output the logically inverted signal as a clock signal A.
The control signal SEL is input to an inverter 443 to output the logically inverted signal as a control signal BB. The control signal BB is input to an inverter 444 to output the logically inverted signal as a control signal B.
In normal operation, the control signal SEL=0 (L level) is set to set the control signal BB=1 and the control signal B=0. Thus, the transmission gate 401 of the selector 40 is turned on to output the input signal D to the master latch 41.
In a scan test, the control signal SEL=1 (H level) is set to set the control signal BB=0 and the control signal B=1. Thus, the transmission gate 402 of the selector 40 is turned on to output the input signal SIN to the master latch 41.
The master latch 41 comprises a transmission gate 411 for enabling/disabling an output from the selector 40, and an inverter 412 for inverting and outputting an output from the transmission gate 411. An inverter 413 for inverting and outputting an output from the inverter 412, and a transmission gate 414 for connecting/disconnecting the output of the inverter 413 to/from the input of the inverter 412 are series-connected between the input and output of the inverter 412.
The inverters 412 and 413 and transmission gate 414 constitute a latch. An output from the inverter 412 is output to the subsequent slave latch 43 via a transmission gate 415.
The slave latch 43 comprises an inverter 431 for inverting and outputting an output from the master latch 41, an inverter 432 for inverting and outputting an output from the inverter 431, and a transmission gate 433 for connecting/disconnecting the output of the inverter 432 to/from the input of the inverter 431. The inverters 431 and 432 and transmission gate 433 constitute a latch, and an output from the slave latch 43 is output as an output signal Q.
Operation in a scan test will be explained with reference to FIGS. 6A to 6I.
In a scan test, the control signal SEL=0 (FIG. 6B) is set to turn on the transmission gate 402 (FIG. 6C). In this state, for a clock signal CLK=0, e.g., before time T1 (FIG. 6A), the clock signal AB=1 and the clock signal A=0 hold. In the master latch 41, the transmission gate 411 is turned on (FIG. 6D) to input the scan logic input signal SIN (FIG. 6H) from the selector 40 to the inverter 412.
At time T1, the clock signal CLK=1 is set to set the clock signal AB=0 and the clock signal A=1. Thus, the transmission gate 411 is turned off, and the transmission gate 414 is turned on (FIGS. 6D and 6E) to latch an output from the inverter 412.
At this time, the transmission gate 415 is also turned on (FIG. 6F) to input an output from the inverter 412 to the slave latch 43. Then, the inverter 431 outputs the inverted output as the output signal Q (FIG. 6I). At time T2, the clock signal CLK=0 is set to latch the output signal Q by the slave latch 43 (FIG. 6G).
The conventional scan flip-flop circuit comprises the selector 40 for selecting either one of the normal logic input signal D and scan logic input signal SIN by the external control signal SEL depending on normal operation or scan test. Even in normal operation, this selector 40 exists on the path of the normal logic input signal D to delay propagation of the input signal D, failing to operate the scan flip-flop circuit at a higher speed.